The dilemma here is that for years, digital and analog designers have been trained differently, on completely separate tool sets.

No one wants to start over and train on a completely new set of tools. Training time and initial investments are tough calls. But growth of the high-bandwidth communications technology sector has spurred the demanding complexities of today's A/MS chips.

Companies that wish to remain competitive are shifting their technology paradigms in order to stay on top.

STMicroelectronics Inc., Intel Corp. and the leading wireless communications companies are standardizing on top-down design using the new analog HDLs, such as VHDL-AMS and Verilog-A, for mixed-signal design.

There are many reasons. First, the complexities of today's designs make traditional schematics difficult, if not impossible, to use.

Second, system-level design, particularly mixed-signal design and partitioning, is a leading culprit in schedule delays.

Analog and digital subsystems have for the most part been created separately and have not been tested for potentially faulty interaction until fabrication. These days, no one can afford the expense and time-to-market delays that result from such a mistake.

The increasing adoption of language-based design tools does not mean that digital or analog designers will be expected to abandon all of their traditional methods and learn an entirely new approach to design. Rather, these tools have been created to complement existing tools without requiring months of retraining.

For example, many designers are trying to create low-cost digital CMOS designs with analog components. People creating these “big D/littleA" designs will find that VHDL-AMS or Verilog A are relatively easy to incorporate into their existing design flows. For the highest performance, the analog HDLs must be used in concert with behavioral-model libraries and language-independent simulators.

Behavioral-model libraries mimic the behavior of a device at several levels of abstraction. Each model also offers parameters that enable almost unlimited customization; and if a model is not available, an analog HDL, like VHDL-AMS, can be used to create new custom code.

The trends toward partnerships and purchased intellectual property are making it necessary to use language-independent simulators that can accept Verilog, Verilog-AMS, VHDL,VHDL-AMS, Spice and C-level models.

Such simulators let designers reuse portions of the analog or digital testbench in the full-chip verification. The models created this way are great starting models for the next generation of product and tend to improve with each successive generation.

Designers responsible for mixed-signal chips will need to investigate such mixed-signal design options in order to stay at the head of the pack. The initial learning curve is the investment needed to bridge the gap. It is my belief that both analog and digital designers will find that these tools make their jobs significantly easier in the coming years.